Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures. These architectures are named for the resemblance that the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuits, respectively.
In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The control gates of each floating gate memory cell of the array matrix are connected to select lines (which are often referred to as rows and/or word lines) and their drains are connected to column bit lines. The source of each floating gate memory cell is typically connected to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their control gates. The row of selected memory cells then place their stored data values on the column bit lines by flowing a differing current if in a programmed state or not programmed state from the connected source line to the connected column bit lines.
FIG. 1 shows a portion of a typical prior art NAND flash memory array. The selected word line 100 for the flash memory cells being programmed is typically biased by programming pulses that start at a voltage of around 16V and may incrementally increase to more than 20V. The selected word line 100 of the cells 101-103 to be programmed is biased at 19V. The unselected word lines for the remaining cells are biased at Vpass. This is typically in an approximate range of 9-10V. The bit lines of the cells 101-103 to be programmed are biased at 0V while the other bit lines are inhibited (i.e., biased at VCC).
As NAND flash memory is scaled, parasitic capacitance coupling between the selected word line and adjacent word lines becomes problematic. Because of the parasitic coupling, the neighboring cells are more prone to program disturb than the other cells that also share the common bit line with the cells being programmed. This causes the cells on neighboring wordlines to experience program disturb.
The program disturb condition has two operation modes: boosting mode and Vpass mode. During the boosting mode, the cell's channel is at a positive boosting voltage (e.g., 6V) with respect to the gate and the gate is at Vpgm (e.g., 19V). During the Vpass mode, the cell's channel is at ground and the gate is at Vpass (e.g., 10V). In FIG. 1, the cells 120, 121 on the selected word line 100 and inhibited bit lines are influenced by boosting mode program disturb. The neighboring cells 110-118 that are coupled to the enabled bit lines experience Vpass mode program disturb.
Increasing Vpass to try to reduce the disturb condition actually makes the condition worse for some cells. For example, the source and drain regions of one uninhibited bit line of memory cells 103, 112, 115, and 118 are coupled to 0V due to the 0V program biasing on the bit line. If Vpass is only 10V on the unselected word lines, the source and drain regions are coupled to 9V. However, if Vpass were raised to a higher voltage (e.g., 15V), the source/drain regions would also be coupled up to a higher voltage, thus increasing the program disturb on that bit line.
Program disturb is also degraded as the number of program/erase cycles increase. As the quantity of program/erase cycles increase, the voltage difference between the programmed state and the erased state narrows. This makes the affected cells more susceptible to over-programming as the threshold voltage distributions narrow.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce the effects of program disturb in a memory device.